The present invention relates to the manufacture of semiconductors and, more specifically, to a semiconductor with a low dielectric constant material between intermetallic leads and a process for manufacturing such semiconductors.
In semiconductor chip design, the various micro-electrical components that comprise the working components of an integrated circuit are connected together by metal interconnects. The metal interconnects are typically made of copper, aluminum, or some alloy of those metals. The various micro-electrical components include, for example, transistors, capacitors, resistors, and the like.
As complementary metal oxide semiconductor (CMOS) chips (typically silicon) have become more complex, both on-chip interconnects and associated fabrication processes have become critical to the performance, reliability, and cost of integrated circuits. For example, the needs for higher performance and lower cost per chip for successive CMOS generations have led to linear increases in the number of devices, but quadratic increases in the number of interconnects.
To improve the signal speed of logic chips, it is necessary to reduce the dielectric constant of the insulator between the metal lines. Silicon dioxide has preferentially been used as the insulator because it has superior mechanical strength and electrical and chemical integrity. In addition, silicon nitride and silicon dioxide-silicon nitride composites have also been preferred over other insulators because they have excellent insulation properties and low defect levels. These insulators exhibit a high dielectric constant, however, which hinders signal speed.
Recently, attempts have been made to replace the conventional silicon dioxide, silicon nitride, and silicon dioxide-silicon nitride composites with low dielectric constant materials as the dielectric material insulator. Examples of such materials include silicon containing low dielectric constant organic materials, silicon containing low Kappa dielectric (silk, a product of the Dow Corp.), diamond-like carbon, and aerogels (which use microscopically small trapped air bubbles to lower the dielectric constant). The use of low dielectric constant materials reduces the capacitance between the lines (or leads), thus reducing the RC time constant (i.e., the time constant for a series connection of a resistor R and a capacitor C). Unfortunately, these low dielectric insulators cause significant problems. For example, low dielectric materials often have inferior mechanical strength and reduced chemical and thermal conductivity compared to silicon dioxide.
The deficiencies of the conventional processes of reducing the dielectric constant of the insulator between metal lines show that a need still exists for a process which reduces the dielectric constant of the insulator but also retains the mechanical and chemical properties of silicon dioxide. To overcome the shortcomings of the conventional processes, a new process is provided. An object of the present invention is to provide a process for fabricating a semiconductor having a low dielectric constant material between intermetallic leads such that the low dielectric constant material improves signal speed versus typical silicon dioxide, silicon nitride, or silicon dioxide-silicon nitride composite insulators. Another object of the present invention is to provide a semiconductor having a low dielectric constant material between intermetallic leads which exhibits superior mechanical strength and electrical and chemical integrity over conventional low dielectric material insulators.
To achieve these and other objects, and in view of its purposes, the present invention provides a semiconductor device having a planar integrated circuit interconnect which has a reduced dielectric constant. The circuit interconnect comprises a dielectric material between two levels of line wires, in which the dielectric material has dummy vias filled with a low dielectric material.
The invention also provides a process of fabricating the circuit interconnect described above. The process comprises the following steps. First, a substrate having a first line wire is formed. Next, a dielectric layer is formed on the substrate. A second line wire is then formed in the dielectric layer. Next, a contact via is formed in the dielectric layer which interconnects the first and second line wires. A dummy via, which is filled with a low dielectric material, is then formed. The dummy via extends into the dielectric layer such that it does not contact the first or second line wires.
A second embodiment of the process of the present invention comprises the following steps. First, a substrate is provided having a first line wire formed in the substrate. A dielectric layer is then formed on the substrate. Next, a plurality of recesses are formed which extend into a portion of the dielectric layer, forming precursor contact vias and dummy vias. The recesses are then filled with a low dielectric material. Next, a line wire trench is formed in the dielectric layer such that it does not contact the dummy vias but does contact the precursor contact vias. The precursor contact vias are then etched to the first line wire. Next, the precursor contact vias and line wire trench are filled with a metal, forming contact vias and a second line wire. The final result is a planar integrated circuit interconnect that can be repeated as needed to form the desired number of stacked interconnects.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.